Speculative pre-execution assisted by compiler (SPEAR)

A Low-Complexity Issue Queue Design with Speculative Pre-execution

Current superscalar architectures inherently depend on an instruction issue queue to achieve multiple instruction issue and out-oforder execution. However, the issue queue is implemented as a centralized structure and mainly causes globally broadcasting operations to wake up and select the instructions. Therefore, a large issue queue ultimately results in a low clock rate along with a high circ...

A low-complexity microprocessor design with speculative pre-execution

Current superscalar architectures strongly depend on an instruction issue queue to achieve multiple instruction issue and out-of-order execution. However, the issue queue requires a centralized structure and mainly causes globally broadcasting operations to wakeup and select the instructions. Therefore, a large issue queue ultimately results in a low clock rate along with a high circuit complex...

Support for Software Assisted Speculative Execution

Computer architects strive to improve machine performance by exploiting parallelism, but control flow and data dependences limit available parallelism. Speculative execution enhances parallelism by selectively ignoring the constraints of control flow and data dependences, thereby executing instructions before it it known whether they are needed or correct. Software assisted speculative executio...

Compiler Support 3.1 Speculative Execution 3.2 Compiler Assisted Synthesis of Algorithm-based Checking in Multiprocessors 3

Compiler Support for Dynamic Speculative Pre-Execution

Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), which contains the future probable cache miss instructions and backward slice, can run on the spare hardware context for data prefetching. Recently, various forms of speculative pre-execution have been developed, including...